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University: University of Edinburgh
Sector(s): Financial Services, Electronics, Sensors & Photonics
Innovation in Financial Computing
This configuration description for a computing engine delivers the capability to process complex financial models in a fraction of the time required by existing software approaches. When implemented in reconfigurable hardware (Field Programmable Gate Array – FPGA) it enables the effective use of high performance computing for Monte-Carlo simulation models of chance events, such as option pricing.
Uncertainty involved in financial modelling means that mathematical techniques are a critical tool. Monte-Carlo simulations are important for financial applications, including bond pricing, risk analysis and market prediction, and can be used to simulate various sources of uncertainty that affect the value of the instrument, portfolio or investment under consideration. This approach involves large number of independent variables and is, therefore, computationally intensive. Microprocessor-based solutions are not well suited to dealing with this complexity, resulting in long processing times and associated high levels of power consumption.
Reconfigurable hardware, such as FPGAs, offers the high performance of a dedicated hardware algorithm implementation, with a fraction of the area and power consumption of equivalent micro-processor based solution. This Monte-Carlo based simulation engine for option pricing offers significant performance enhancement with the added advantage of re-programmability. The speed up is due to exploitation of high levels of process parallelisation and intelligent FPGA block design.
An FPGA hardware implementation of the Monte-Carlo simulation core for the GARCH pricing model of European options has been demonstrated to result in 340x speed up compared with equivalent software implementations. This speed up is scalable to a multi-FPGA solution and is independent of the number of nodes used.
Copyright in source code
Development Status: Proof of concept
Key Publication: Benkrid et al, Engineering Letter, 2008, 16, 3, 434-442
A licence to the source code for FPGA configuration is available from the University of Edinburgh.
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